Stacked ICs with vertical interconnect containing fine-pitch micro-bumps and through-silicon vias (TSVs) are a hot-topic in design and manufacturing communities. These 2.5D- and 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, testing for manufacturing defects remains an obstacle and potential showstopper before 3D-SICs can become a reality. There are concerns about the cost or, even worse, feasibility of testing such TSV-based 3D chips. In this basic tutorial, we present key concepts in 3D technology, terminology, and benefits. We discuss design and test challenges and emerging solutions for 2.5D- and 3D-SICs. Topics to be covered include an overview of 3D integration and trendsetting products such as a 2.5D-FPGA and 3D-stacked memory chips, test flows and test content for 3D chips, advances in wafer probing reported by probe companies, modular testing and design-for-test architectures, and ongoing IEEE P1838 standardization efforts for test access.

We start by briefly looking at trends in process, design, and analog/mixed-signal testing, then in more detail at trends in ad hoc design-for-test (DfT) and analog defect simulation. We then review standardized DfT suitable for mixed-signal circuits, including IEEE 1149.1, .4, .6, .8, and 1687. The trend analysis concludes with an analysis of BIST techniques, especially for ADC/DAC, but also for PLL, SerDes, DDR, and miscellaneous analogue. Next, seven essential principles of practical analog BIST are discussed, ranging from testing the BIST itself, and adding for precision, to subtracting for accuracy, and generating a digital result. Lastly, we discuss the most practical techniques to use in new DfT and BIST circuitry, ranging from the classic analog test bus, to mostly-digital oversampling and undersampling circuits that improve measurement range, resolution, and reusability, to ultimately optimize quality and cost of test.

Hardware security is an important optimization objective for designs (similar to power, performance, reliability and testability). We will highlight why hardware security and trust are as important as these other objectives from the economics of security, IP protection and counterfeiting perspectives. We will then describe the simple gotchas when traditional DFT and validation techniques are used (scan chains, JTAG, SoC test, assertion based validation). Next, we will outline how traditional DFT techniques can be used to improve hardware security and trust. Finally, we will present �Design for Trust� approaches that can provide testability without compromising security and trust.

Stacked ICs with vertical interconnect containing fine-pitch micro-bumps and through-silicon vias (TSVs) are a hot-topic in design and manufacturing communities. These 2.5D- and 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, testing for manufacturing defects remains an obstacle and potential showstopper before 3D-SICs can become a reality. There are concerns about the cost or, even worse, feasibility of testing such TSV-based 3D chips. In this advanced tutorial, we present an overview of 3D technology, terminology, and benefits, and provide detailed coverage of 2.5D/3D test challenges and emerging solutions. Attendees are expected to have some familiarity with and understanding of 2.5D/3D test techniques. Topics to be covered include: (i) 3D test access architectures with emphasis on logic-on-logic chips, memory-on-logic chips with JEDEC wide-I/O, DfT for 2.5D chips, and EDA flows and industry case studies for automated DfT insertion and test generation; (ii) DfT optimization and repair techniques, including 2.5D ICs and memory stacks; (iii) innovations in wafer probing and alternatives to probing for pre-bond test; (iv) 3D test-cost modeling and test-flow selection.

Many of today�s electronic devices communicate with other devices using a highspeed asynchronous serial links such as: Ethernet, USB, Firewire, PCI-Express, XAUI, SONET, SAS, etc. Such devices make use of a serializer-deserializer transmission scheme called SerDes. In the past, device-to-device communications operated on a synchronous clocking scheme, such as the standard EIA-232 or RS-232 serial bus. While synchronous buses are finding fewer and fewer applications in these data communication applications, they remain the most popular approach for communicating within an IC. This tutorial will begin by describing the attributes of both synchronous clock signals and those signals transmitted asynchronously over a serial channel. In the case of synchronous clock signals, both time and frequency domain descriptions of the clock signal will be described. This includes various time-domain jitter metrics, like periodic jitter and cycle-to-cycle jitter, accumulated jitter, and frequency-domain metrics like phase noise. For asynchronous systems, there is less emphasis on the clock behavior and more emphasis on the quality of the signal transmission expressed in terms of its bit-error rate (BER). While BER is the ultimate performance metric for system engineers, the time required to capture this measure is often too long to perform in production. As a result, alternative approaches are necessary. For the most part, these methods are based on jitter decomposition techniques, i.e., probabilistic methods that describe the underlying structure of the randomness present with the asynchronous signal. Commonly used jitter terms such as random, deterministic and total jitter abbreviated to RJ, DJ and TJ metrics will be described using the concept of a Gaussian mixture model. This tutorial will conclude with a discussion of several DSP-based test techniques used to quantify jitter transmission from the system input to its output. This includes a discussion about jitter transfer function test and a jitter tolerance test. Some discussion of DFT methods for jitter extraction will also be given. These will be presented from a time-domain signal processing perspective.

Partly because of design outsourcing and migration of fabrication to low-cost areas across the globe, and partly because of increased reliance on third-party intellectual property (3PIP), the integrated circuit (IC) supply chain is now considered far more vulnerable than ever before. Among the related concerns, this tutorial focuses on the problems of hardware Trojans and counterfeit ICs. Malicious circuit modifications, known as hardware Trojans, provide additional functionality which is unknown to the designer and user, but which can be exploited by the perpetrator after deployment to sabotage or incapacitate a chip, or to steal sensitive information. Similarly, counterfeit ICs constitute a growing problem in the semiconductor industry, jeopardizing reliability and robustness of the applications wherein they are deployed. Such ICs can be either used devices which have been reclaimed and reintroduced in the supply chain as new, reverse-engineered, over-produced, or simply fake. This tutorial outlines the challenges and elucidates the various multi-disciplinary research solutions associated with certifying trustworthiness and genuineness of ICs.

This tutorial covers fundamental concepts, recent developments and industry practices on validating and testing integrated circuits for speed failures. The intended audience is a combination of semiconductor industry practitioners, EDA technologists, and researchers in digital test. The tutorial starts with a discussion on defects and design marginalities that induce a circuit to fail at its rated speed while passing at a lower speed. This is followed by fault models and fault sensitization conditions, for classical faults such as transition and path delay, and for marginalities such as crosstalk, voltage droop, multiple-input switching and charge-sharing. Subsequently, concepts in test generation and fault simulation for delay faults are discussed. Recent advances in delay test specific DFT techniques, timing-aware metrics for test quality, and techniques to improve DPPM (defective parts per million) and reduce yield loss, are described. Finally, industry case studies that apply delay test concepts in post-silicon validation, speed binning and in-field reliability are discussed.

Hierarchical design has come a long way in a very short time. The use of multi-level hierarchical test methodologies is, therefore, ramping up. Design teams use these architectures to handle the explosion in design size, liberal use of 3rd-party IPs, and the general use of multi-level hierarchical design (core, block, sub-chip, SOC) methodologies across geographically dispersed corporations and their design partners. To support these types of designs with appropriate DFT, design teams leverage IEEE standards-based methodologies to implement test in a hierarchical manner, across heterogeneous cores types (memories, logic, AMS, interface IP, and legacy cores). These hierarchical DFT design styles support DFT closure, power reductions during test, isolated debug and diagnosis, pattern porting, capacity improvements, and uniform and ubiquitous access. Using IEEE test standards such as 1149.1 and 1500 promote benefits such as these. CTL and STIL support these methodologies. The future P1687 is meant to allow instrumentation access, supported by test portability throughout the device life cycle. This tutorial covers these trends, design styles and methodologies, and how they are facilitated by IEEE test standards.

Integrated circuits have traditionally all been tested identically in the manufacturing flow with little sharing of test results between the different test insertions. However, as the detection of subtle manufacturing flaws becomes ever more challenging and expensive in aggressively scaled nanometer technologies, innovative new statistical screening methods are being developed that attempt to improve test effectiveness and optimize test costs by subjecting �suspect� parts to more extensive testing, and also adaptively bring in additional tests that target the suspected failure modes. Adaptive test methods also support the dynamic reordering of test to achieve early failure detection resulting in significant savings in test application time. This tutorial presents an overview of these emerging test methodologies, and illustrates their effectiveness with results from a number of published experimental studies on volume production digital and analog circuits. Commercial tools offered by some of the new companies that have emerged in the "Adaptive Test" space will also be discussed.

Many sources of noise complicate the translation of circuit designs from concept to hardware. Process variation skews timing so that only a percentage of parts reach the desired power/performance targets. Voltage and temperature variation, induced by environmental and workload changes, requires additional operating margin which also affects power/performance. Over time the parts age and degrade, again affecting power/performance. Fortunately, many of these affects occur on a timescale where they can be measured and mitigated with the appropriate circuits. This tutorial will provide circuit level instruction on the design, implementation, testing, and uses of noise following hardware. Topics covered are: noise processes; circuits for measuring and compensating for noise; techniques for dynamic operating point control; and testing, calibration, and qualification challenges. Much of the tutorial will be based on the constant timing margin controller developed in the Power7+ microprocessor with appropriate additions from the current art covering alternative methods.

Moderns electronic systems are increasingly demanded in safety-critical contexts where reliability and dependability are key factors in exigent Service Level Agreements. To successfully meet such challenges, the electronic devices must be fully qualified, characterized and eventually improved. The objective of this tutorial is to provide useful and practical background information about Single Event Effects (SEEs) affecting the safety of automotive, biomedical and avionic/space applications. An excursus on the SEE terminology, characteristics and metrics for advanced digital logic, including relevant sources for ground level applications will be provided. The tutorial investigates the Soft Error Rate (SER) testing, evaluation and prediction methodologies from process and cell-level fault considerations to the higher-abstraction system-level failure effects, including the evaluation of quantitative parameters such as SER, Failure-in-Time (FIT) and Byte Error Rate (BER) to qualitative parameters (failure criticality, SDC, etc). Furthermore, various approaches, recommendations and strategies are discussed to help the designer implement high-quality circuits and systems. Dedicated process and standard-cell level techniques such as rad-hard cells, DICE, cell layout improvement, will be presented in addition to circuit-level approaches: SIHFT, processor Lock-step, DWC, TMR, selective-TMR and many others. The presentation will naturally follow with overall reliability-improvement methods (SEE-aware synthesis, map, place and route strategies), dedicated tool chains, high-level (system, software, protocol techniques). Finally, all the technological and methodology aspects are discussed in relation to concrete and practical examples of industrial-case studies including (but not limited to): Xilinx SRAM-based and Microsemi Flash-based FPGAs for space and avionics, NVIDIA GP-GPUs neutron effect analysis, automotive Pirelli CyberTyre system, high-reliability network designs and General Motors (GM) engine control units.

The push for portable, battery-operated, and �cool-and-green� electronics has elevated power consumption as the defining metric of integrated circuit (IC) design. Testing ICs built for such applications requires judicious consideration of test power implications on various aspects of the design cycle (e.g., packaging and power grid design), test engineering (multi-site ATE power supply limitations and board design), power-aware test planning (DFT and ATPG), and developing the enabling EDA tool infrastructure (SW for estimation, reduction and low-power test generation). Physically-aware low-power test techniques are also becoming important for accuracy and hot-spot minimization, especially for designs at 22nm and below. Furthermore, with power optimization and power management techniques becoming �de-facto� in almost all 45nm and lower chips, systematic testing of these structures and the device in the presence of these structures becomes mandatory. This tutorial is intended to provide an overview of low-power IC testing covering (a) dimensions of power-aware testing, (b) methods for test power analysis and signoff, (c) techniques for controlling test power consumption and (d) test of power managed designs. Case-studies illustrating industrial design deployment practices and existing EDA vendor support will also be outlined.

With the wide adoption of nanometer technologies and increasing amount of embedded memories, it has become crucial for today�s SOCs to use advanced memory test and repair solutions. These solutions provide comprehensive detection of not only random defects, but also systematic and process variation defects often manifested under unique test corners. Moreover, with the adoption of FinFET technologies, these advanced solutions are extended to cover new FinFET specific defects. This tutorial, besides addressing these defect detection topics, will cover an end-to-end BIST and repair architecture to handle tens of thousands of embedded memory instances in today�s SOC, while taking into account power management constraints, functional timing implications, test scheduling flexibility, and area minimization options. With the proliferation of high-density packaging technologies, such as 2.5D and 3D-ICs, this tutorial will also cover testing and diagnosis external memory dies and interconnects, via an advanced BIST engine residing in the neighboring SOC die, in same high-density package. This tutorial will also address post-silicon analysis and yield optimization trade-offs using volume diagnostic, failure coordinate calculation, defect classification, reconfiguration and repair.

This tutorial teaches the principles of various data mining approaches and their respective learning techniques. The approaches include classification, regression, transformation, feature ranking, clustering, novelty detection, rule learning and similarity search. We will illustrate the working principles of various learning techniques such as tree learning, random forest, neural network, support vector machine, Gaussian process, rule learning, etc. We will discuss application examples to illustrate how various learning approaches can be applied in test and verification. The experience of developing a practical data mining flow will be explained. We will show how data mining in practice implements an iterative knowledge discovery process. Promises of this knowledge discovery paradigm will be demonstrated through positive results based on several industrial application settings.

Yield has become the defining metric for success and failure for Semiconductor Manufacturing at leading edge technologies. The yield challenge has largely been driven the confluence of the design complexity and the advanced process and packaging technologies/materials. In addition, the factory (Fab) environment and the equipment toolset have also become significant contributors to the yield equation. The solution requires a strong collaborative teamwork approach involving Designer/customer, Equipment provider and the Factory engineering and operations teams to ensure first time yield success, product quality and profitability.

As components continue to scale with Moore�s Law, complexity scales as well. Given that a system is comprised of a hierarchy of sub-systems, where components are at the bottom of the hierarchy, one could claim that at a system level scaling is exponential to Moore�s Law. A �system� can be anything that is in between an iPhone and IBM�s Watson. While these two �systems� seem quite diverse, there are plenty of similarities from a test perspective. This tutorial will begin with a description of what exactly is a �system� and what are the elements that comprise a system (including software). We will talk about the hierarchical architecture of a system and the test process around that hierarchy. The majority of the tutorial will focus on testing and diagnosis at the system level (both functional and application based testing). This will include both online and offline testing, as well as validation testing, production testing and reliability testing. The tutorial will look at both traditional and innovative test techniques.